1. Field of the Invention
The present invention relates generally to imaging sensors, and more particularly to an imaging system-on-chip solution for enhancing and controlling dynamic range, while maintaining high sensor performance.
2. Description of the Related Art
Visible imaging systems implemented using CMOS imaging sensors significantly reduce camera cost and power while improving resolution and reducing noise. The latest cameras use CMOS imaging System-on-Chip (iSoC) sensors that efficiently marry highly competitive image sensing with ancillary components including timing controller, clock drivers, reference voltages, A/D conversion and key signal processing elements. High-performance video cameras can hence be constructed using a single CMOS integrated circuit supported by only a lens and battery. These improvements translate into smaller camera size, longer battery life, and applicability to new cameras that simultaneously support still capture and high definition video.
The advantages offered by system-on-chip integration in CMOS visible imagers for emerging camera products have spurred considerable effort to further improve active-pixel sensor (APS) devices. Active-pixel sensors with on-chip analog and/or digital signal processing can provide temporal noise comparable or superior to scientific-grade video systems that use CCD sensors. Complicated CMOS active-pixel circuits, on the other hand, usually have higher fixed pattern noise (possibly requiring additional iSoC or camera circuitry to suppress the noise), lower quantum efficiency, and limited image sensor scalability to higher resolution using smaller pixel pitch.
FIG. 1 is a block diagram for a representative CMOS imaging SoC of the prior art described by Chen (Proceedings of 10th International Conference on Pattern Recognition, 16-21 Jun. 1990, vol. 2, page(s): 286-291). While Chen teaches iSoC integration including A/D converter per column and signal processing with supporting memory, dynamic range is limited by the signal chain from the pixel through the A/D converter. U.S. Pat. No. 6,456,326 (FIG. 2) subsequently included the correlated doubling sampling taught by White (1973 International Solid State Circuits Conference, pp. 134-135, 208-209) to reduce reset kTC noise and improve instantaneous dynamic range. Pixel Array 300 in the '326 patent is further supported by timing controller 302 in conjunction with horizontal logic 320 and vertical logic 310 to generate electronic images at the READ node. Those skilled in the art will appreciate that FIG. 3 is a representative timing diagram for such imaging sensors including Chen and the '326 patent although, for simplicity, we assume an imaging sensor having four rows.
Each frame's image is formed on a line-by-line/row-by-row basis so that the imaging sensor has a so-called “rolling shutter.” In other words, there is a built-in latency of one line time between each row of the sensor since reading and resetting of each row is handled line-by-line. Over the course of each frame time for the full frame integration outlined in FIG. 2, the top line actually finishes integrating just as the bottom line begins integrating that frame's image. Maximizing the period during which the entire array is actively integrating hence requires the standard extended frame timing shown in FIG. 3. Concern over the latency and the general trend for greatly increasing sensor noise, with even modest increases in data rate, has prevented other designs from leveraging the line-by-line nature of imaging sensor readout to actually boost performance.
U.S. Pat. No. 7,046,284 discloses a modern high-performance low-noise CMOS imaging system comprising a low noise pixel array supported by high-performance column buffers and high-speed, low-power A/D conversion co-located in the sensor such that the effective transmission path between the final high-speed analog video driver (column buffer, line driver or programmable gain amplifier) and the A/D converter acts as a resistor, rather than a reactance. The high-performance column buffer design, such as disclosed in U.S. Pat. No. 5,892,540 and herein incorporated by reference, minimizes column-based fixed pattern noise while competently handling the signal from each pixel on a column-by-column basis. The read out circuit for each column of pixels includes a high gain, wide bandwidth, CMOS differential amplifier, a reset switch and selectable feedback capacitors, selectable load capacitors, correlated double sampling and sample-and-hold circuits, optional pipelining circuit to simultaneously process multiple rows, and an offset cancellation circuit connected to an output bus to suppress the input offset non-uniformity of the wideband amplifier supplying the signal to the high-speed A/D converter. The system may further include both an analog gain amplifier stage and a digital programmable amplifier stage. While the resulting imaging System-on-Chip generates still images or video with at least 12-bit resolution, even wider dynamic range is desired to surpass the exposure latitude of photographic film. This requirement mandates further evolution in the CMOS iSoC architecture to deliver more bits per image frame without requiring support from the camera's signal processor.
Several schemes exist in the prior art for enhancing dynamic range using alternative pixel implementations incorporating in-pixel digitization, noise filtering, multiple storage sites, self-reset, variable capacitance and gamma modification, among others. Representative disclosures for these inventions respectively include U.S. Pat. Nos. 5,461,425; 6,504,141; 6,078,037; 6,963,370; 7,091,531, and 7,141,841. Unfortunately, higher circuit complexity in the pixel often increases fixed pattern noise thereby negating any effective boost in capacity. The prior art also teaches systemic solutions requiring camera processing to broaden dynamic range. These typically rely on processing multiple images at two or more exposure times; hence, they add significant cost to the camera bill of materials (BOM) via additional memory, memory controllers and advanced signal processing.